Interrupts from external devices, such as the timer, are fed to predefined input lines of an Interrupt Controller (Intel 1990; Wang 2015) which prioritizes the interrupt inputs and routes the interrupt with the highest priority as an interrupt request (IRQ) to the CPU. At the end of each instruction execution, if the CPU is not in the state of accepting interrupts, i.e. it has interrupts masked out in the CPU’s status register, it will ignore the interrupt request, keeping it pending, and continue to execute the next instruction. If the CPU is in the state of accepting interrupts, i.e. interrupts are not masked out, the CPU will divert its normal execution sequence to do interrupt processing. For each interrupt, the Interrupt Controller can be programmed to generate a unique number, called an interrupt vector, which identifies the interrupt source. After acquiring an interrupt vector number, the CPU uses it as an index to an entry in an Interrupt Vector Table (AMD64 2011) in memory, which contains a pointer to the entry address of an Interrupt handler, which actually handles the interrupt. When interrupt processing finishes, the CPU resumes normal execution of instructions.
Source: Wang K.C. (2018), Systems Programming in Unix/Linux, Springer; 1st ed. 2018 edition.